Experimental work | Troubleshooting ICL 7667 mosfet driver

1:06 PM

Recently while i was having work with mofet driver ic ICL7667 i noticed that it gets hot  with the output open circuited (not connected to MOSFET). I posted my question in a linkedin group and got the following answers.





Circuit i tried 


  1. The ICL7667 is tricky as it is specified. If you use it in a grounded MOSFET drive (ie V- = GND, most common use) there should not be any problems. If an input is grounded, then the input circuit will not draw any current. Any unused drivers should have grounded inputs to minimize the IC's current draw. Each input greater than 1.5V will dissipate <=30 mW @15V depending upon the duty cycle. Now, the way the part is specified, the V- can go to as low as -18V (abs). The input threshold is +1.5V above V-, which means that the driving source of the 7667 must also be V- based. This may present a problem with the input and output ESD protection diodes. Please carefully review your surrounding drive system.  Lastly, if your input drive circuit has long trace lengths, and/or your driver bypass capacitor is too large and if your driving frequency is relatively high, the input PCB (with PCB inductances and capacitances), will form a transmission line all the way to the 7667's output MOSFETs isolation wells. These wells are typically 300 pF for this age device. If you model the input DC supply lines as a transmission, you could have a supply voltage of + 3 to 8V above your VDD line due to these transmission line effects. The transmission line effects cause more failures within MOSFET drivers than any other cause (EOS). Periodic avalanching occurs because of the output isolation wells within the device causing heating and eventual failure of the device. If you would like me to send you a whitepaper discussing these transmission line effects that I wrote, I would be happy to. (or download it on ResearchGate, author: Marty Brown). Great question Hadeed. Many engineers assume that MOSFET gate drivers are bullet proof. They have a serious weakness, if the surrounding circuit is not designed properly. I did a though failure analysis of failed gate drivers (including failed die photos) for a prominent power supply manufacturer who had several inches of input signal length to the driver. All operating conditions were well within abs ratings, and the transmission line effects over-voltaged the outputs of the drivers. We do need some more information about the operating conditions (Vdd, Vee, Fsw, etc). We have some of the finest diagnostians in the world on this site who know more than just the part is not plugged-in. The local driver bypass capacitor is too large. It should be no more than a 0.1 uF. Any larger, you will get very large voltage spikes on the output MOSFETs within the driver. The extra heat could be the power dissipation due to the avalanching occurring on the output FETs. There is a series resonant tank circuit formed with the Bbypass and the Cwell (500pF) in series with 6 NH (bondwires) on the VCC and Cee lines plus the external trace inductances (VDD and Vee). The capacitors form a capacitive voltage divider. The smaller capacitor (Cwell) will develop a higher transient spike in inverse proportion to the capacitive ratios. Ypu could have several volts appearing on top of the Vdd voltage. I am sorry for the former short written response, life always has a way of getting in the way. Now I have time. This posting is for everyone who uses MOSFET drivers (integrated or separate). Other than blatent disregard of the design rules, the transmission line effects are the leading killer of MOSFET drivers (EOS - electrical over stress). I had done a deep dive on a low but significant MOSFET driver failure rate at a prestigious power supply customer. I teamed with a Si design engineer (a wizard in my eyes) to probe and record the actual signals upon the die. He was puzzled from a pins-in perspective, and I was equally puzzled from an application (pins-out) perspective. A 3 micron biCMOS gate driver (1990's tech) failing within a circuit that was comfortably within the device's operating specification. What we found, between our two expertises, was completely dumbfounding. The Vdd drain voltages of the output MOS devices were experiencing a +8v to +15V only due to the transmission line effects on the power supply lines. This caused the slow heating of the output devices and a latent failure in the output devices. The design of the wells surrounding the output FETs had a great influence of the FET's survival. That is, the number of tie-down vias between the well and the substrate. A charge concentration occurred if there were too few tie downs. To reduce the problem additional well tie-downs were added (4 to 8). This only reduced the die overvoltage problem. It is still there but the design was much more robust. Now, back to your part of the situation, As described above, as counter intuitive as it is, a too large of a local driver bypass capacitor will eventually cause your MOSFET driver to fail. First you have to examine the amount of gate charge your power MOSFET exhibits during each transition. Then the bypass capacitor should not exceed 10-30 times that charge in its storage capacity. Or the bypass capacitor should be no more than 10 - 30 times the Ciss of the MOSFET. That makes an optimum local bypass capacitor no larger than 0.1 uF. The PCB layout also has a large influence upon the situation. The local bypass capacitor should be at the end of the driver IC and the traces between the bypass capacitor and the Vcc and Vee pins should run beneath the driver IC and be closely parallel to each other. The trace magnetic fields of the high di/dts would then tend to chancel each other out. If you could make a custom gate driver PCB footprint with a ceramic bypass capacitor, I would greatly recommend it.There is actually a way for us pins-out engineers to view this effect within a dual gate driver, such as the ICL7667. Connect the unused input such that its output is high. Connect your scope probe to the output of the unused driver (as bad as typical voltage probes are for noise). and look at the transition times when driving the other driver circuit. You will view the actual internal Vcc bus within the device. You really need a 50 ohm probe for this measurement, but the over the counter voltage probes will give you a good idea as to what is going on. The problem is real, and engineers are totally unaware of its existence. The gate driver is the keystone between the sensitive control circuit and the butt-kicking power circuits. Treat it nicely and gently. The other choice is a cascading OV failure within the system. You may have a defective or damaged part. If you ground the input of the active driver and it still heats-up, then throw it out. I think a fresh part is well warranted for your attention. (answer by Marty Brown)
  2. This smells to me like a connection error. Hadeed, could we see a schematic of how it's connected (hand-drawn is fine) and a photo showing the interconnect? . After this i uploaded the schematic shown above. Then the reply came as.. It's a simple circuit and the schematic looks good. My next question is: how hot does it get? Switching at 200Khz, I expect the device to heat up, but not too much. Can you hold your finger on it? If so, maybe the heat dissipation you're seeing is normal. If it's too hot to touch, then I agree, something is wrong. (answer by Ken Coffman) 
  3. The reason your chip is heating up is that you grounded both the input and the output (pin 5) of the unused driver. (answer by Darrel hambley).
  4. We would need a little more information from you to really help... What are your power supply voltages (V+ & V-), are you allowing your inputs to float while the output is disconnected, have you grounded the NC pins on the package? You should note that the data sheet does not mention the recommended connection for the NC pins, at the risk they are connected to the body of the internal FETs I would leave those floating. Second, on the data sheet page 5 right column about a quarter of the way down, Intersil states that the inputs should NEVER be left floating between Vih & Vil as this can cause the IC to remain in high current mode. You should also follow the guidelines about return path routing as the hot loop in this IC can cause unwanted common impedance.You should also connect a 2.2nF capacitor from each output to the same supply at V- for testing. This will emulate a large FET. Make sure to use an appropriately rated ceramic capacitor and not an electrolytic or tantalum. (Answer by Cody Tudor)
  5. I disconnected the output pin 5 but still my IC was heating up. In testing i burnt one.. The NC pins i.e Pin1 and 8 are left unattended. I tried grounding them too but does not make any difference. The input was supplied from the function generator at 50 % duty ratio. What does this exactly mean that input shld never be floating specially if the input pin has a connection with the output of function generator. (I replied this)

Solution : 

Unfortunately the IC was not available in the locaq market of Riyadh. I found a substitute and it worked at the end. 

Share This Story

Tags: , , ,

You Might Also Like

2 comments

Copyright statement

Copyright © 2015-2017 by Hadeed A Sher

All rights reserved. No part of this blog may be reproduced, distributed, or transmitted in any form or by any means, including photocopying, recording, or other electronic or mechanical methods, without my prior written permission. For permission requests, write to the blog author addressed “Attention: Permissions Coordinator,” at the contact form.


Disclaimer

This blog is about my PhD work and an archive to my engineering education. However, additional study material for the courses i teach and that i have studied is also archived here.
All the circuits in this blog are tested by myself under specific conditions. BE CAREFUL if you are experimenting them, the blogger and this blog are not responsible to any harm and or damage to yourself and your equipment.


Contact form

Name

Email *

Message *